1. Field of the Invention
The present invention relates to a structure and manufacturing method of a semiconductor device including a trench isolation structure for providing isolation between active device formation regions (referred to "active region" hereinafter) formed at the main surface of a semiconductor substrate. Particularly, the present invention relates to a structure and a manufacturing method of a semiconductor device including a trench isolation structure suitable for preventing generation of an inverse narrow channel effect when applied in a VLSI (Very Large Scale Integrated circuit).
2. Description of the Background Art
As a conventional element isolation technique in a VLSI, a trench isolation structure is employed that isolates active regions on a main surface of a semiconductor substrate by burying an insulation film into a trench provided at the main surface. The method of manufacturing a conventional trench isolation structure disclosed in pp. 28.1.1.about.28.1.4 in IEDM 94-671 will be described hereinafter with reference to FIGS. 28A-28C and FIGS. 29A-29C.
In this conventional method of manufacturing a trench isolation structure shown in FIG. 28A, a thermal oxide film 2, a silicon nitride film 3, and an oxide film 4 are formed in a stacked manner on a silicon substrate 1. Then, an opening 5 is formed in these layered films at a position corresponding to an isolation region where a trench is to be formed. Formation of opening 5 is effected by a patterning process according to photolithography, dry etching, and the like.
Using this pattern including opening 5 as a mask, silicon substrate 1 is selectively etched to form a trench 6 where an isolation region is to be provided as shown in FIG. 28B. Then, thermal oxidation is applied to form a thermal oxide film 7 at the inner wall of trench 6 (FIG. 28B). Then, as shown in FIG. 28C, trench 6 is filled with an oxide film 8 by TEOS (Tetra Ethyl Ortho Silicate glass) method. Since the aspect ratio of trench 6 prior to the formation of oxide film 8 is high in the current integrated circuits scaled to higher densities, trench 6 must be filled with an oxide film that is not dense such as a TEOS oxide film in order to avoid the generation of a void. Then, as shown in FIG. 29A, planarization is carried out by means of etching, mechanical abrasion, or chemical abrasion with silicon nitride film 3 as a stopper. FIG. 29B shows the structure where silicon nitride film 3 exposed by the planarization process is removed. Then, thermal oxide film 2 is removed by wet etching, and oxide film 8 is planarized. Then, a gate oxide film 9 is formed on silicon substrate 1. A gate electrode is formed thereupon to result in the structure shown in FIG. 29C.
In a MOS (Metal Oxide Semiconductor) transistor, the so called narrow channel effect where the threshold voltage increases according to reduction of the channel width is generally encountered. In a trench isolation structure, an electric field is concentrated in the proximity of the edge of the trench isolation (around point A shown in FIG. 29C) when a voltage of the level of approximately the threshold value is applied to the gate electrode, whereby a parasitic channel is formed in the proximity of the trench isolation edge. Current will flow through the parasitic channel formed at the sidewall of the trench to result in a lower threshold voltage. This phenomenon where the threshold voltage is reduced as the channel width becomes smaller is called an inverse narrow channel effect. This inverse narrow channel effect is also called "hump phenomenon" from the fact that a hump is generated in the drain current of the subthreshold characteristics.
This inverse narrow channel effect has becomes a significant problem in a semiconductor device including a trench isolation structure since it causes variation in the threshold voltage, which in turn induces degradation of the subthreshold characteristics.